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ISL21009
Data Sheet February 14, 2007 FN6327.1
PRELIMINARY
Precision, Low Noise FGATM Voltage References
The ISL21009 FGATM voltage references are extremely low power, high precision, and low noise voltage references fabricated on Intersil's proprietary Floating Gate Analog technology. The ISL21009 features very low noise (4VP-P for 0.1Hz to 10Hz), low operating current (180A, Max), and 3ppm/C of temperature drift. In addition, the ISL21009 family features guaranteed initial accuracy as low as 0.5mV This combination of high initial accuracy, low drift, and low output noise performance of the ISL21009 enables versatile high performance control and data acquisition applications with low power consumption.
Features
* Output Voltages . . . . . . . . . . . . . . . 1.25V, 2.500V, 5.000V * Initial Accuracy . . . . . . . . . . . . . .0.5mV, 1.0mV, 2.0mV * Input Voltage Range. . . . . . . . . . . . . . . . . . . . Up to 16.5V * Output Voltage Noise . . . . . . . . . . 4uVP-P (0.1Hz to 10Hz) * Supply Current . . . . . . . . . . . . . . . . . . . . . . . .180A (Max) * Temperature Coefficient . . . 3ppm/C, 5ppm/C, 10ppm/C * Output Current Capability. . . . . . . . . . . . . . . . . . . . 7.0mA * Operating Temperature Range. . . . . . . . . -40C to +125C * Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC * Pb-Free Plus Anneal Available (RoHS Compliant)
Available Options
VOUT OPTION (V) 1.250 1.250 1.250 2.500 2.500 2.500 5.000 5.000 5.000 INITIAL ACCURACY (mV) 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 TEMPCO. (ppm/C) 3 5 10 3 5 10 3 5 10
Applications
* High Resolution A/Ds and D/As * Digital Meters * Bar Code Scanners * Basestations * Battery Management/Monitoring * Industrial/Instrumentation Equipment
PART NUMBER ISL21009BFB812Z Coming Soon Coming www..com ISL21009CFB812Z Soon ISL21009DFB812Z Coming Soon ISL21009BFB825Z ISL21009CFB825Z ISL21009DFB825Z ISL21009BFB850Z ISL21009CFB850Z ISL21009DFB850Z
Pinout
ISL21009 (8 LD SOIC) TOP VIEW GND or NC 1 VIN 2 DNC 3 GND 4 8 DNC 7 DNC 6 VOUT 5 TRIM or NC
Pin Descriptions
PIN NUMBER 1 4 2 6 5 3,7,8 PIN NAME GND or NC GND VIN VOUT TRIM DNC DESCRIPTION Can be either Ground or No Connect Ground Connection Power Supply Input Connection Voltage Reference Output Connection Allows user trim typically 2.5%. Leave Unconnected when unused. Do Not Connect; Internal Connection - Must Be Left Floating
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL21009 Ordering Information
PART NUMBER (Note) ISL21009BFB825Z ISL21009BFB825Z-TK ISL21009CFB825Z ISL21009CFB825Z-TK ISL21009DFB825Z ISL21009DFB825Z-TK ISL21009BFB850Z ISL21009BFB850Z-TK ISL21009CFB850Z ISL21009CFB850Z-TK ISL21009DFB850Z ISL21009DFB850Z-TK NOTES: A) Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 B) Add "-T" suffix for tape and reel PART MARKING 21009BF Z25 21009BF Z25 21009CF Z25 21009CF Z25 21009DF Z25 21009DF Z25 21009BF Z50 21009BF Z50 21009CF Z50 21009CF Z50 21009DF Z50 21009DF Z50 VOUT OPTION (V) 2.500 2.500 2.500 2.500 2.500 2.500 5.000 5.000 5.000 5.000 5.000 5.000 GRADE 0.5mV, 3ppm/C 0.5mV, 3ppm/C 1.0mV, 5ppm/C 1.0mV, 5ppm/C 2.0mV, 10ppm/C 2.0mV, 10ppm/C 0.5mV, 3ppm/C 0.5mV, 3ppm/C 1.0mV, 5ppm/C 1.0mV, 5ppm/C 2.0mV, 10ppm/C 2.0mV, 10ppm/C QUANTITY PER TEMP. REEL/TUBE RANGE (C) 100 1000 100 1000 100 1000 100 1000 100 1000 100 1000 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC PKG. DWG. # M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15
1 +5V C1 10F 2 3 4
GND VIN NC GND ISL21009-25
NC NC VOUT NC
8 7 6 5
SPI BUS X79000 1 2 3 4 5 6 7 8 9 10 SCK A0 A1 A2 SI SO /RDY UP DOWN OE /CS CLR VCC VH VL VREF VSS VOUT VBUF VFB 20 19 18 17 16 15 14 13 12 11 LOW NOISE DAC OUTPUT C1 0.001F
FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUBRANGING DAC
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ISL21009
Absolute Voltage Ratings
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Max Voltage VIN to Gnd . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +18V Max Voltage VOUT to Gnd (10s). . . . . . . . . . . . . . -0.5V to VOUT +1V Voltage on "DNC" pins . . . . No connections permitted to these pins. Lead Temperature, soldering (10s) . . . . . . . . . . . . . . . . . . . . +260C ESD Ratings (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV (CBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . -40C to +125C
Thermal Information
Continuous Power Dissipation (TA = +70C) 8 Ld SOIC derate 5.88mW/C above +70C. . . . . . . . . . . . . 471mW Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp TA = -40C to +125C, unless otherwise specified. MIN -0.5 -1.0 -2.0 TYP MAX +0.5 +1.0 +2.0 3 5 10 50 2.0 2.5 10 100 60 4 2.2 60 UNIT mV mV mV ppm/C ppm/C ppm/C ppm/1kHrs % mA s dB VP-P VRMS nV/Hz
Common Electrical Specifications (ISL21009-25, -50)
PARAMETER VOA DESCRIPTION VOUT Accuracy @ TA = +25C ISL21009B ISL21009C ISL21009D TC VOUT Output Voltage Temperature Coefficient (Note 1) ISL21009B ISL21009C ISL21009D VOUT/t Long Term Stability (Note 4) Trim Range ISC tR Short Circuit Current (Note 3) Turn on Settling Time Ripple Rejection eN VN Output Voltage Noise Broadband Voltage Noise Noise Density TA = +25C
CONDITIONS
TA = +25C, VOUT tied to Gnd VOUT = 0.1% f = 10kHz 0.1Hz f 10Hz 10Hz f 1kHz f = 1kHz
Electrical Specifications (ISL21009-25, VOUT = 2.50V)
PARAMETER VOUT VIN IIN VOUT /VIN DESCRIPTION Output Voltage Input Voltage Range Supply Current Line Regulation 3.5V < VIN < 5.5V
VIN = 5.0V, TA = -40C to +125C, unless otherwise specified. MIN TYP 2.500 3.5 95 50 10 10 20 100 16.5 180 150 50 50 100 MAX UNIT V V A V/V V/V V/mA V/mA ppm
CONDITIONS
5.5V < VIN < 16.5V VOUT/IOUT Load Regulation Sourcing: 0mA IOUT 7mA Sinking: -7mA IOUT 0mA VOUT/TA Thermal Hysteresis (Note 2) TA = +125C
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ISL21009
Electrical Specifications (ISL21009-50, VOUT = 5.0V)
PARAMETER VOUT VIN IIN VOUT /VIN VOUT/IOUT DESCRIPTION Output Voltage Input Voltage Range Supply Current Line Regulation Load Regulation 5.5V < VIN < 16.5V Sourcing: 0mA IOUT 7mA Sinking: -7mA IOUT 0mA VOUT/TA NOTES: 1. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the temperature range; in this case, -40C to +125C = +165C. 2. Thermal Hysteresis is the change of VOUT measured @ TA = +25C after temperature cycling over a specified range, TA. VOUT is read initially at TA = +25C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25C. The difference between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For TA = +165C, the device under test is cycled from +25C to +125C to -40C to +25C. 3. Guaranteed by device characterization and/or correlation to other device tests. 4. FGA voltage reference long term drift is a logarithmic characteristic. Changes that occur after the first few hundred hours of operation are significantly smaller with time, asymptotically approaching zero beyond 1,000 hours. Because of this decreasing characteristics, long term drift is specified in ppm/1kHrs. Thermal Hysteresis (Note 2) TA = +125C 5.5 95 20 10 20 50 VIN = 10.0V, TA = -40C to +125C, unless otherwise specified. MIN TYP 5.000 16.5 180 90 60 100 MAX UNIT V V A V/V V/mA V/mA ppm
CONDITIONS
Typical Performance Curves (ISL21009-25) (REXT = 100k)
140 115A 120 100 IIN (A) 80 60 40 20 0 3.5 5.5 7.5 9.5 VIN (V) 11.5 13.5 15.5 80 3.5 5.5 7.5 9.5 VIN (V) 11.5 13.5 15.5 81A IIN (A) 110 105A +25C +125C 120
100 -40C 90
FIGURE 2. IIN vs VIN 3 UNITS
FIGURE 3. IIN vs VIN, 3 TEMPERATURES
VOUT (V) (NORMALIZED TO 2.50V at VIN = 5V)
2.50010 (NORMALIZED TO VIN = 5.0V) 115A 2.50005 2.50000 81A 2.49995 2.49990 2.49985 2.49980 3.5 DELTA VO (V) 105A
60 40 20 0 -20 -40 -60 -80 -100 3.5 5.5 7.5 9.5 11.5 VIN (V) 13.5 15.5 +125C -40C +25C
5.5
7.5
9.5 11.5 VIN (V)
13.5
15.5
FIGURE 4. LINE REGULATION
FIGURE 5. LINE REGULATION OVER TEMPERATURE
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ISL21009 Typical Performance Curves (ISL21009-25) (REXT = 100k)
0.10 0.08 DELTA VOUT (mV) 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 +25C -40C VOUT (V) +125C
(Continued)
2.5002 2.5001 2.5000 2.4999 2.4998 2.4997 2.4996 2.4995 2.4994 2.4993 -40 -20 0 20 40 60 80 100 120 140 UNIT 2 UNIT 1 UNIT 3
SINKING
OUTPUT CURRENT (mA)
SOURCING
TEMPERATURE (C)
FIGURE 6. LOAD REGULATION
FIGURE 7. VOUT vs TEMPERATURE
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 1 10 100 1k 10k 100k 1M 10M 100nF 10nF 1nF 500kHz PEAK VIN (DC) = 10V NO LOAD
FREQUENCY (Hz)
FIGURE 8. PSRR AT DIFFERENT CAPACITIVE LOADS
FIGURE 9. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
5.2 4.8 4.4 4.0 3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 0
VIN HIGH IIN
VIN AND VOUT (V)
MEDIUM IIN LOW IIN 0.05 0.1 0.15 0.2 TIME (ms) 0.25 0.3 0.35 0.4
FIGURE 10. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
FIGURE 11. TURN ON TIME
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FN6327.1 February 14, 2007
ISL21009 Typical Performance Curves (ISL21009-25) (REXT = 100k)
(Continued)
GAIN IS x1000, NOISE IS 4Vp-p 160 140 120 ZOUT () 100 80 60 40 20 0 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 1nF NO LOAD 100nF 10nF
FIGURE 12. ZOUT vs FREQUENCY
FIGURE 13. VOUT NOISE, 0.1Hz to 10Hz
NO OUTPUT CAPACITANCE 50A
NO OUTPUT CAPACITANCE
7mA
-50A
-7mA
FIGURE 14. LOAD TRANSIENT RESPONSE
FIGURE 15. LOAD TRANSIENT RESPONSE
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ISL21009 Typical Performance Curves (ISL21009-50) (REXT = 100k)
140 112A 120 100 IIN (A) 100 95A IIN (A) 80 60 40 20 0 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) 80 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) +125C 90 -40C 104A 110 +25C
FIGURE 16. IIN vs VIN 3 UNITS
FIGURE 17. IIN vs VIN, 3 TEMPERATURES
VOUT (V) (NORMALIZED to 5.0V AT VIN = 10V)
5.0001 VO (V) (NORMALIZED TO VIN = 10.0V) 5.0000 4.9999 4.9998 104A 4.9997 4.9996 4.9995 4.9994 5.5 95A 112A 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V)
100 0 -100 -200 -300 -400 -500 -600 -700 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) +25C +125C -40C
FIGURE 18. LINE REGULATION
FIGURE 19. LINE REGULATION OVER TEMPERATURE
0.10 0.05 0.00 VOUT (mV) -0.05 -0.10 -0.15 -0.20 -0.25 -7 -6 -5 SINKING -4 -3 -2 -1 0 1 2 3 OUTPUT CURRENT (mA) 4 567 SOURCING +125C +25C -40C
FIGURE 20. LOAD REGULATION
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ISL21009 Typical Performance Curves (ISL21009-50) (REXT = 100k)
5.001 NORMALIZED TO 25C 5.001 VOUT (V) 5.000 UNIT 2 5.000 4.999 4.999 4.998 -40 UNIT 3 -20 0 20 40 60 80 100 120 140 UNIT 1 PSRR (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 1k 10k 100k 1M 10M 100nF 1nF 10nF VIN (DC) = 10V VIN (AC) RIPPLE = 50mVP-P NO LOAD
(Continued)
TEMPERATURE (C)
FREQUENCY (Hz)
FIGURE 21. VOUT vs TEMPERATURE
FIGURE 22. PSRR AT DIFFERENT CAPACITIVE LOADS
VIN = 10V VIN = 1V
VIN = 10V VIN = 1V
FIGURE 23. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
FIGURE 24. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
12 VIN (V) AND VOUT (V) 10 ZOUT (W) 8 6 4 2 0 0 270nA 50 VIN 450nA
120 1nF 100 80 60 NO LOAD 40 20 340nA 0 100 150 TIME (s) 200 250 300 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10nF
FIGURE 25. TURN ON TIME
FIGURE 26. ZOUT vs FREQUENCY
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ISL21009 Typical Performance Curves (ISL21009-50) (REXT = 100k)
GAIN IS x1000, NOISE IS 4Vp-p
(Continued)
50A
-50A
FIGURE 27. VOUT NOISE, 0.1Hz to 10Hz
FIGURE 28. LOAD TRANSIENT RESPONSE
7mA
-7mA
FIGURE 29. LOAD TRANSIENT RESPONSE
Applications Information
FGA Technology
The ISL21009 voltage reference uses floating gate technology to create references with very low drift and supply current. Essentially the charge stored on a floating gate cell is set precisely in manufacturing. The reference voltage output itself is a buffered version of the floating gate voltage. The resulting reference device has excellent characteristics which are unique in the industry: very low temperature drift, high initial accuracy, and almost zero supply current. Also, the reference voltage itself is not limited by voltage bandgaps or zener settings, so a wide range of reference voltages can be programmed (standard voltage settings are provided, but customer-specific voltages are available).
The process used for these reference devices is a floating gate CMOS process, and the amplifier circuitry uses CMOS transistors for amplifier and output transistor circuitry. While providing excellent accuracy, there are limitations in output noise level and load regulation due to the MOS device characteristics. These limitations are addressed with circuit techniques discussed in other sections.
Micropower Operation
The ISL21009 consumes extremely low supply current due to the proprietary FGA technology. Low noise performance is achieved using optimized biasing techniques. Supply current is typically 95A and noise is 4VP-P benefitting precision, low noise portable applications such as handheld meters and instruments.
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FN6327.1 February 14, 2007
ISL21009
Data Converters in particular can utilized the ISL21009 as an external voltage reference. Low power DAC and ADC circuits will realize maximum resolution with lowest noise.
VIN = 3.5V 10F 0.1F VIN VO ISL21009 GND 0.01F 10F 2k
Board Mounting Considerations
For applications requiring the highest accuracy, board mounting location should be reviewed. The device uses a plastic SOIC package which will subject the die to mild stresses when the PC board is heated and cooled and slightly changes shape. Placing the device in areas subject to slight twisting can cause degradation of the accuracy of the reference voltage due to these die stresses. It is normally best to place the device near the edge of a board, or the shortest side, as the axis of bending is most limited at that location. Mounting the device in a cutout also minimizes flex. Obviously mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy.
FIGURE 30. HANDLING HIGH LOAD CAPACITANCE
Turn-On Time
The ISL21009 devices have low supply current and thus the time to bias up internal circuitry to final values will be longer than with higher power references. Normal turn-on time is typically 100s. This is shown in Figure 11. Circuit design must take this into account when looking at power up delays or sequencing.
Noise Performance and Reduction
The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 4VP-P. The noise measurement is made with a bandpass filter made of a 1 pole high-pass filter with a corner frequency at 0.1Hz and a 2-pole low-pass filter with a corner frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth. Noise in the 10kHz to 1MHz bandwidth is approximately 40VP-P with no capacitance on the output. This noise measurement is made with a 2 decade bandpass filter made of a 1 pole high-pass filter with a corner frequency at 1/10 of the center frequency and 1-pole low-pass filter with a corner frequency at 10 times the center frequency. Load capacitance up to 1000pF can be added but will result in only marginal improvements in output noise and transient response. The output stage of the ISL21009 is not designed to drive heavily capactive loads, so for load capacitances above 0.001F the noise reduction network shown in Figure 30 is recommended. This network reduces noise significantly over the full bandwidth. Noise is reduced to less than 20VP-P from 1Hz to 1MHz using this network with a 0.01F capacitor and a 2k resistor in series with a 10F capacitor. Also, transient response is improved with higher value output capacitor. The 0.01F value can be increased for better load transient response with little sacrifice in output stability.
Temperature Coefficient
The limits stated for temperature coefficient (tempco) are governed by the method of measurement. The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures, take the total variation, (VHIGH - VLOW), and divide by the temperature extremes of measurement (THIGH - TLOW). The result is divided by the nominal reference voltage (at T = +25C) and multiplied by 106 to yield ppm/C. This is the "Box" method for specifying temperature coefficient.
Output Voltage Adjustment
The output voltage can be adjusted up or down by 2.5% by placing a potentiometer from Vout to ground, and connecting the wiper to the TRIM pin. The TRIM input is high impedance, so no series resistance is needed. The resistor in the potentiometer should be a low tempco (<50ppm/C) and the resulting voltage divider should have very low tempco <5ppm/C. A digital potentiometer such as the ISL95810 provides a low tempco resistance and excellent resistor and tempco matching for trim applications.
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FN6327.1 February 14, 2007
ISL21009 Typical Application Circuits
VIN = +5.0V R = 200 2N2905
VIN ISL21009 VOUT VOUT = 2.50V GND 2.5V/50mA 0.001F
FIGURE 31. PRECISION 2.5V 50mA REFERENCE
+3.5 to 16.5V 0.1F 10F
VIN VOUT ISL21009-25 VOUT = 2.50V GND
0.001F VCC RH + EL8178 - RL VOUT (BUFFERED) VOUT (UNBUFFERED)
X9119 SDA 2-WIRE BUS SCL VSS
FIGURE 32. 2.5V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE
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FN6327.1 February 14, 2007
ISL21009
+3.5 to 16.5V 0.1F 10F
VIN VOUT ISL21009-25 GND + -
EL8178 VOUT SENSE LOAD
FIGURE 33. KELVIN SENSED LOAD
+3.5 to 16.5V 0.1F
10F
VIN VOUT ISL21009-25 TRIM GND
2.5V 2.5%
VCC I2C BUS SDA SCL ISL95810 VSS
RH
RL
FIGURE 34. OUTPUT ADJUSTMENT USING THE TRIM PIN
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FN6327.1 February 14, 2007
ISL21009 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
a
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN6327.1 February 14, 2007

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